1. Field of the Invention
The invention relates to simulating the printing of a pattern onto a wafer and in particular to simulating accurate resist and etch edges.
2. Description of the Related Art
Simulation is the process of predicting a real phenomenon with a set of mathematical formulas, i.e. models. Advanced computer-implemented tools can simulate complex processes, such as integrated circuit (IC) fabrication. In simulating IC fabrication, a simulation tool can use one or multiple models with an input IC design to generate simulation results. Simulation results can be used to modify certain elements, parameters, and/or conditions of fabrication, thereby improving the performance of the IC. For example, simulations can be performed to optimize a layout before fabricating a mask and its corresponding wafer. Logically, having accurate simulation results facilitates making the appropriate changes to the layout and/or mask.
A simulation tool can provide different types of outputs. A first type of simulation output includes a three-dimensional mapping of the intensity in the image plane: I=f(x,y,z), where x and y are the coordinates perpendicular to the optical axis of the stepper and z is the coordinate along the optical access of the stepper. For a given intensity level I0 and a given focal position zo, a contour of the image can be generated, I0=f(x,y,z0). This contour is called a simulated optical image.
FIG. 1A illustrates a simulator 104 that can receive layout data 102 representing a layout 101 for generating a simulated optical image 105. Simulator 104 can also receive lithography conditions input 103, which can indicate the lithography conditions under which one or more physical masks for reproducing layout 101 on a wafer of an integrated circuit are to be exposed. Lithography conditions can include, for example, the wavelength of illumination (λ), the numerical aperture (NA), the partial coherency value (σ), the defocus (i.e. focal plane positioning), the exposure level, on/off-axis illumination, lens aberrations, substrate conditions, etc. In one embodiment, lithography conditions input 103 can include a range of these conditions such that the simulation can be performed a number of times for different combinations of these conditions. In this manner, layout data 102 of layout 101 can be analyzed over a range of possible lithography conditions.
Using lithography conditions input 103 and layout data 102, simulator 104 can quickly generate simulated optical image 105, which simulates a wafer being patterned by the masks reproducing layout 101. However, simulator 104 uses very limited input information regarding the resist or etch processes. For example, in one embodiment, simulator 104 merely uses a threshold for the resist in its model(s) to generate simulated optical image 105.
To increase the accuracy of the simulated optical image, additional information regarding the resist and etch processes can be used. For example, in addition to lithography conditions input, a simulator could also receive resist/etch measurements input. In one embodiment, resist/etch measurements can be obtained by exposing a mask, which includes various test patterns, to various lithography conditions that could be used during actual integrated circuit fabrication. The printed features on the corresponding test wafer can then be analyzed for the effects of those lithography conditions on the actual resist/etch profiles of such features.
An atomic force microscope (AFM) can be used for such analysis. An AFM includes a probe with a highly sensitive tip, which can be used to measure the topography of the wafer's surface. In one embodiment, called a contact mode AFM, the tip can be dragged over the surface of the wafer. The probe measures the force applied to the tip by the surface of the wafer, i.e. the greater the height of the resist/etch profile, the greater the force applied to the tip. In another embodiment, called a non-contact mode, the probe can sense Van der Walls attractive forces between the tip and the wafer surface without actually dragging the tip over the wafer's surface.
Another tool for measuring topography is the scanning tunneling microscope (STM). The STM includes a sharp tip connected to a piezoelectric scanner. A small bias voltage can be applied to the wafer. When the tip is brought sufficiently close to the surface of the biased wafer, i.e. within approximately one nanometer, a tunneling current starts to flow between the tip and the wafer. This tunneling current is extremely sensitive to changes in separation of the tip and the wafer. Thus, the STM can measure topography by sensing the variation in tunneling current as the tip is moved over the surface of the wafer.
Yet another tool for measuring topography is the scanning electron microscope (SEM). The SEM uses a beam of high energy electrons, which are focused through a series of electromagnetic lenses, to create a magnified image of the scanned sample, i.e. the wafer surface. Specifically, as the focused electron beam hits the wafer, secondary as well as backscattered electrons are ejected from the wafer. A detector can detect these secondary/backscattered electrons, convert those electrons into corresponding voltages, and apply the voltages to a CRT. Thus, the resulting image of the CRT includes spots of varying intensity, which correspond to the topography of the wafer.
Note that any device capable of providing accurate topography information can be used to measure actual resist/etch profiles of printed features on the wafer. The SEM, which is readily available and easy to use, is generally considered the standard for metrology in most fabrication facilities. However, the measurements output by the SEM are meaningful only if the SEM is calibrated for a given height/elevation of the printed features on the wafer. Moreover, even if the STM or the AFM is used (either of which could provide measurements from various heights/elevations), typically measurements are taken from only one height to build the models. As will be described in further detail below, having limited height/elevation information to build the models can result in some ambiguity in accurately simulating an edge of a feature.
FIG. 2 illustrates a printed wafer 200 including a plurality of printed test patterns 201. Each test pattern can include a set of features of different shapes, critical dimensions (CDs), and feature proximities (i.e. densely populated or isolated). In one embodiment, each test pattern 201 includes identical features, which were exposed to distinct lithography conditions.
Note that in an actual wafer, hundreds of test patterns could be printed by exposing and stepping a reticle across the wafer. Of importance, lithography conditions can be varied for each test pattern. Moreover, each test pattern on the reticle could include thousands or even tens of thousands of features. Therefore, an analysis of a single printed wafer can provide ample resist/etch measurements for building models.
Note that additional wafers can be printed if the range of test patterns and/or lithography conditions increases past the physical limit of a single wafer. For example, different wavelengths of illumination could be used to generate different test wafers. Moreover, various resist and/or etch parameters may be used on different wafers. Resist parameters can include thickness, contrast, pre-bake time, post-bake time, development time, photoresist concentration, developer solution concentration, and light absorption of the resist among others. The etch parameters can include etching time, etching method, and concentration among others.
FIG. 1B illustrates a simulator 106 that can receive lithography conditions input 103 as well as resist/etch measurements input 107 (which could be provided by measuring the resist/etch profiles from printed wafer 200) to generate a simulated calibrated image 108. Note that simulated calibrated image 108 should be more accurate than simulated optical image 105. However, even the calibrated models used by simulator 106 assume that the edges of the features are anisotropically formed. For example, FIG. 1C illustrates an assumed profile 110 of simulated calibrated image 108 at a cut line 109. Assumed profile 110 has vertical sidewalls because, as previously described, the models used by simulator 106 are built using measurements taken from one height/elevation of the wafer.
In actual fabrication, an edge can have significant deviations from a vertical sidewall. To obtain further information regarding these deviations, certain profile simulators can be used. These profile simulators, which can be implemented by the SAMPLE™ tool from University of California, Berkeley or the PROLITH™ toolkit from Finle Technologies, Inc., a subsidiary of KLA-Tencor Corporation, can generate resist and/or etch profiles using pure simulation models that take into account optical as well as resist/etch parameters. The resist/etch parameters could include the complex refractive index of the resist, the dose that the resist gets as a function of depth (wherein because of reflection from the substrate, a standing waves effect occurs), the composition of the resist, the development of the resist, the composition of the material underlying the resist, and the etching of that material. Unfortunately, these calculations are extremely time intensive. Therefore, in a production environment, resist/etch profiles are effectively limited to very small analysis areas. Moreover, these calculations, despite their complexity, still cannot completely capture resist/etch behavior. For example, even subtle variations in chemistry or fabrication environments (e.g. temperature) can dramatically impact processing results. Therefore, the resist/etch profiles generated by the profile simulators can be prone to significant inaccuracy.
Therefore, a need arises for a simulated image generator that can provide an accurate resist/etch edge in a time efficient and cost effective manner.